Multi-Channel PWM Generator IP Core (Verilog)

Overview

This is a fully parameterized and scalable PWM Generator IP Core written in Verilog. It supports multiple channels, dead time insertion, phase shifting, and independent control per channel — while using shared logic to stay resource-efficient.

Whether you’re building a motor driver, inverter, or LED dimmer, this IP is ready to plug into your FPGA project.

Features

• Supports multiple PWM channels
• Independent duty cycle and phase control
• Dead time insertion for high/low side safety
• Shared timing logic for efficiency
• Works with Xilinx Vivado and other Verilog flows
• Simulation testbench included
• MIT Licensed — use it freely or in commercial projects

Included Files

• rtl/pwm_generator_multi.v — RTL source
• sim/tb_pwm_generator_multi.v — testbench
• README.md — usage instructions
• LICENSE — MIT license

Compatibility

• Works on Xilinx 7-series, Artix-7, Spartan, Zynq, and similar FPGAs
• Synthesizable, clean Verilog (no vendor lock-in)
• Easy to integrate into Vivado, ISE, or third-party tools

Support

If you need help integrating or customizing the IP, feel free to reach out — I'm happy to help!